Former Intel CEO Pat Gelsinger is backing a startup developing a high-bandwidth memory architecture designed to combine the speed of SRAM with the density of DRAM. According to The Register, Gelsinger is backing the effort through Playground Global, the venture capital firm where he became a partner in 2025 following his ouster from Intel.
Nagare Labs was founded by Georgia Institute of Technology researchers, and is developing a new memory technology called Z2RAM architecture designed to address one of the biggest constraints facing artificial intelligence infrastructure: the growing gap between processor performance and memory speed.
The technology targets the so-called memory wall, a growing problem in AI systems in which processors can perform calculations faster than conventional memory architectures can supply the required data. The result is a bottleneck where the CPU and GPU are left waiting, for lack of a better word, for the memory to catch up.
A workaround came in the form of high bandwidth memory (HBM), first developed by AMD in 2008, which put the memory on the CPU/GPU die right next to the processor rather than on DIMM sticks on the motherboard. This improved performance but not enough to satisfy data hungry CPUs and GPUs.
That’s where Nagare comes in. Founded by two professors at Georgia Tech whose research has focused on emerging memory technologies and semiconductor devices. The company’s approach uses oxide-semiconductor transistors rather than the capacitors found in conventional DRAM cells.
What they do is essentially increase the density of SRAM, allowing more memory to be packed into the CPU. SRAM is typically used in CPU and GPU caches and is several times faster than DRAM. But it has also much lower capacity, a few megabytes as opposed to gigabytes for DRAM.
A typical DRAM cell stores data using a transistor and a capacitor. Reading the stored charge is destructive, requiring the cell to be refreshed with the data after a read operation. Z2RAM instead uses two transistors, with the gate capacitance of one transistor serving as the charge-storage mechanism. This allows the stored information to be read without draining the charge, potentially reducing latency.
The architecture is also designed to stack memory layers directly above computing logic. Rather than relying on conventional memory stacks connected to processors through an interposer, Nagare aims to integrate memory and logic through a vertically layered structure using oxide-semiconductor processing.
This approach could reduce the distance data must travel between memory and compute, improving bandwidth while lowering the energy required for data movement.
Nagare’s initial design targets memory bit density five times greater than SRAM in a comparable area. That could allow a 64MB SRAM footprint to accommodate approximately 320MB of Z2RAM, according to the company’s technology concept.
Such capacity could be particularly valuable for AI inference, where accelerators must repeatedly access model weights and key-value (KV) caches used to retain information during text generation.
For accelerator designers, the benefits could include fewer memory bottlenecks, lower data-movement energy and improved utilization of processing resources. Larger on-chip memory capacity could also reduce the need to distribute workloads across as many individual accelerators in some applications.
The technology’s proposed vertical scaling is central to its manufacturing strategy. Nagare says its process is intended to build successive memory layers in a manner more closely resembling the vertical fabrication of NAND flash than the assembly of conventional high-bandwidth memory stacks.
If the approach proves practical at scale, it could offer a different route to increasing memory capacity without depending exclusively on smaller transistor geometries or increasingly complex packaging.
