Google Research has completed the 32-bit processor architecture for its open-source Coral neural processing unit (NPU) platform, released a version 1.0 compiler foundation and announced new commercial silicon from Synaptics.

Coral is targeted at energy-efficient AI in wearables, industrial sensors and robotics. The platform is intended to address fragmentation in the edge AI market, where incompatible processor architectures and software toolchains often force developers to rework machine learning models for different chips.

Google’s Coral NPU combines an ML-focused RISC-V architecture with an open software stack, allowing developers to optimize models and deploy them across different system-on-chip (SoC) vendors and power configurations.

The approach is designed to reduce development costs while enabling AI inference directly on devices rather than relying on continuous traffic to and from the cloud. Google said the architecture could support more demanding workloads on battery-powered devices, including compact transformer models, real-time voice translation, spatial audio processing and low-latency visual perception for robots.

The complete Coral package consists of four elements:

  • The complete 32-bit Coral NPU architecture: The architecture includes a new Matrix Execution Unit that can be configured to deliver up to 1 TOPS of performance while targeting an average inference power consumption of 10 mW.
  • The Coral Compiler v1.0, based on IREE/MLIR: An open-source compiler and simulation stack that supports deploying models developed with JAX, PyTorch and TensorFlow to Coral NPU hardware.
  • New MCU chips with Coral NPU: The second-generation Synaptics Astra SR200 series introduces microcontroller chips delivering 400 GOPS of AI performance.
  • New Coralboard kits: Google is introducing the Coralboard SR and expanding global availability of the 1 TOPS Coralboard SL through DigiKey.

The complete 32-bit register-transfer-level (RTL) design is available on GitHub, giving chip developers access to the hardware implementation for integration into custom silicon.

The compiler partitions workloads between the host CPU and NPU, combines compatible operations and organizes matrix computations to fit local memory resources. This hardware/software co-design is intended to reduce the risk that unsupported neural-network operations will fall back to the CPU, increasing latency and power consumption.

Google said its next development phase includes a 64-bit Coral NPU architecture and support for CHERI, a capability-based security technology intended to improve memory safety.

The broader goal is to establish a portable hardware and software platform for edge AI, giving semiconductor companies a reusable accelerator architecture while allowing developers to deploy machine learning workloads across a wider range of power, performance and cost requirements.