Moore’s Law Didn’t End. It Changed Direction

IBM’s “0.7nm chip” is part marketing sleight of hand and part genuine semiconductor breakthrough. Ignore the decimal point. Nanostack—and the decision to build silicon upward—is the real story.

Let’s get the marketing out of the way first.

IBM says it has introduced the world’s first “sub-1 nanometer chip technology.” More specifically, the company calls this a 0.7nm, or 7-angstrom, semiconductor node. That description is guaranteed to generate headlines suggesting IBM has manufactured transistors with features measuring seven-tenths of a nanometer.

It hasn’t.

Modern semiconductor node names stopped corresponding to a particular physical measurement years ago. A 2nm chip does not contain a defining feature that is precisely two nanometers wide, and IBM’s 0.7nm designation does not mean it has somehow manufactured a commercial processor with transistor gates measuring 0.7 nanometers. IBM acknowledges as much in its own announcement, explaining that nodes now refer to a generation of manufacturing technology rather than an exact physical dimension.

This is also not a production processor that IBM is preparing to ship. It is a research demonstration of technologies that IBM believes could provide the foundation for commercial chips in the future. The company says it sees a path to production in as little as five years, which would put the earliest implementation somewhere around 2031. Even that will require a manufacturing partner capable of turning IBM’s laboratory achievement into a repeatable, economically viable, high-volume process.

So yes, “the world’s first 0.7nm chip” is marketing.

But do not let the marketing obscure what IBM has actually accomplished. The decimal point may be doing the promotional work, but the architecture beneath it is real—and potentially far more important.

IBM calls that architecture “nanostack.” It represents a fundamental change in how the semiconductor industry thinks about scaling.

For most of the history of modern computing, Moore’s Law was expressed primarily through horizontal shrinkage. Engineers made transistors smaller so they could place more of them next to one another on a flat piece of silicon. Each new process generation squeezed more computing capability into the same amount of die area, generally delivering better performance, lower power consumption or some combination of the two.

That formula has not stopped working, but it has become extraordinarily difficult and expensive to sustain. The features involved are approaching atomic dimensions. Manufacturing tolerances are narrowing. New fabrication plants cost tens of billions of dollars. Every generation demands more sophisticated lithography, new materials and increasingly complex design techniques.

The semiconductor industry is not running out of ideas. It is running out of room in the directions it has traditionally used.

IBM’s answer is to change direction.

The Z-Axis Arrives

Conventional CMOS designs place N-type and P-type field-effect transistors next to one another. Both are required to form the complementary circuits that make modern processors work, but placing them side by side consumes valuable horizontal area.

Nanostack moves those transistors into the third dimension.

IBM manufactures the transistor layers separately and then bonds the wafers together using what it describes as ultra-thin dielectric bonding. The N-type and P-type transistors can be vertically stacked and staggered rather than occupying adjacent territory on the same plane. Each layer can also be optimized independently, including the use of different channel materials suited to the performance and power characteristics of each transistor type.

This matters for more than density. Separating the transistor layers gives engineers additional freedom to improve one without necessarily compromising the other. IBM says it has experimentally demonstrated the bonding process, dual-channel engineering and functional CMOS inverter operation with the expected switching behavior. In other words, this is not merely a computer rendering of a structure that someone hopes physics will allow. IBM has shown that the structure can be built and can perform actual computation.

That does not make it production-ready, but it moves nanostack beyond a theoretical exercise.

IBM says the resulting architecture can deliver nearly twice the transistor density of its 2021 2nm technology. The company projects as much as 50% higher performance at comparable power or 70% lower energy consumption at comparable performance. IBM also says its semiconductor roadmap based on nanostack could support another decade of scaling.

Those are meaningful numbers. They are also IBM’s projections, not independently verified benchmarks from a commercial processor. There is no nanostack CPU running a data center, no nanostack AI accelerator training a frontier model and no high-volume production line yielding millions of these devices at an acceptable cost.

Why the Distinction Matters

Semiconductor history contains many technologies that worked beautifully on research wafers and struggled when exposed to the brutal economics of commercial manufacturing. Bonding two intricately fabricated wafers requires extraordinary alignment precision. Defects in either wafer can affect the completed structure. Heat must be managed through multiple active layers. Every additional manufacturing step creates another opportunity to reduce yield, increase cycle time and drive up cost.

The question is not only whether IBM can build nanostack transistors. It has shown that it can. The question is whether a foundry can manufacture hundreds of millions—or billions—of them reliably and profitably.

That is where semiconductor breakthroughs become semiconductor businesses.

The SRAM Sleeper Story

The figure I find most intriguing in IBM’s announcement is not the 0.7nm label, the transistor count or even the projected performance improvement. It is IBM’s claim of approximately 40% SRAM scaling.

Static random-access memory is used for cache and other forms of fast, on-chip storage. It sits close to the processing logic so data can be retrieved more quickly than it can from external memory. The problem is that SRAM has not continued shrinking at anything close to the pace of logic. As processors have advanced, cache has consumed an increasing share of the available die area.

That is especially significant for AI.

The AI infrastructure conversation is usually framed as a shortage of mathematical operations. We need more GPUs, more accelerators and more TOPS. But an AI chip’s ability to perform calculations is only useful if the system can deliver data to those compute engines fast enough to keep them occupied.

Moving data between storage, memory and processors takes time and consumes power. Moving it across a chip is better than moving it across a board. Moving it from nearby cache is better still. As AI models grow, memory capacity, memory bandwidth and data movement increasingly determine real-world performance.

This is the memory wall, and it cannot be solved merely by adding more arithmetic units.

If nanostack allows designers to fit substantially more SRAM into the same physical area, it could improve the balance between compute and memory inside future AI accelerators. More data could remain closer to the processing engines. That could reduce latency and energy consumption while improving accelerator utilization.

Forty percent more efficient SRAM scaling will not eliminate the need for high-bandwidth memory or fast interconnects. Nor does it mean every workload will automatically become 40% faster. But it attacks one of the most stubborn constraints in advanced processor design. That makes it much more than a supporting statistic in an announcement about smaller transistors.

It may be the part of IBM’s work that AI chip designers ultimately value most.

About That 9,000-TOPS AI Accelerator

IBM offers an especially dramatic illustration of nanostack’s AI potential. The company says popular AI accelerators today can deliver approximately 1,500 trillion operations per second and estimates that an accelerator built with its 7-angstrom technology could reach roughly 9,000 TOPS. IBM suggests this could reduce a three-month frontier-model training run to a couple of weeks.

It is an effective way to communicate the scale of the ambition. It should not be confused with a benchmark or product commitment.

TOPS is a measure of theoretical operations. Training time is the outcome of an entire system. That system includes memory, networking, storage, software, numerical precision, communication between accelerators, cooling, utilization and the structure of the model being trained.

A sixfold increase in theoretical operations does not automatically make a training cluster six times faster. If the processors spend part of their time waiting for data or synchronizing with other processors, adding more computational capacity can amplify the imbalance rather than eliminate it.

IBM’s projection demonstrates what denser, faster and more efficient silicon might make possible. It does not prove that a model requiring three months to train today will finish in two weeks on a future nanostack system.

That future system does not yet exist.

A Breakthrough for 2031 Will Not Power 2026

The commercialization timeline is particularly relevant because of the enormous bets being placed on AI infrastructure today.

Hyperscalers, model companies, governments and investors are committing trillions of dollars to data centers, accelerators, power generation and transmission capacity. Communities are being asked to accept enormous facilities that can consume as much electricity as small cities. Utilities are planning around demand projections that stretch years into the future.

IBM’s research offers a credible path toward processors that perform more work with less energy. That is welcome news. The AI industry badly needs efficiency improvements throughout the stack.

But nanostack cannot solve the immediate power and infrastructure constraints facing AI in 2026. IBM says the earliest production could occur in approximately five years. Meaningful volume adoption could take longer. The industry cannot reach backward from a promising 2031 technology and use it to validate every data-center assumption being made today.

There is also a rebound effect to consider. More efficient computing has historically not led the world to consume less computing. It has made computing cheaper and encouraged us to use more of it.

A nanostack accelerator that delivers several times the performance per watt might reduce the energy required to run today’s model. It could also make it economically possible to build much larger models, deploy AI in many more places and perform workloads that are currently impractical.

Efficiency can relieve a constraint while simultaneously expanding demand.

IBM’s Semiconductor Business Without the Fabs

There is another story here about IBM itself.

IBM no longer operates the world’s leading commercial semiconductor foundry. It does not need to.

Big Blue has positioned itself upstream in the semiconductor value chain. Its researchers develop materials, transistor structures and manufacturing processes that partners can eventually adapt for commercial production. IBM helped pioneer nanosheet transistor technology, which has since become central to the industry’s leading-edge roadmaps. Nanostack is its candidate for what comes next.

This allows IBM to influence—and potentially license—the semiconductor future without assuming all the capital risk of competing directly against TSMC, Samsung or Intel in high-volume manufacturing. IBM invents part of the roadmap. Someone else spends tens of billions of dollars trying to manufacture it at scale.

That is not a minor role. At a time when semiconductor technology has become an issue of national competitiveness, economic security and military power, the institutions that define how tomorrow’s chips are built may be as strategically important as the companies that fabricate them.

The unanswered question is who will commercialize nanostack.

IBM has not identified the manufacturing partner expected to bring the technology into production. Any foundry attempting it will have to solve the yield, bonding, alignment, thermal and cost challenges that separate a compelling research result from a commercial process node.

Five years is simultaneously a long time in AI and an aggressive timetable in semiconductor manufacturing.

Look Past the Decimal Point

IBM’s announcement should not be reduced to either boosterism or debunking.

The company has not manufactured features smaller than atoms. It has not produced a commercial 0.7nm processor, and it has not demonstrated an AI accelerator delivering 9,000 TOPS. The node name is a generational label selected at least partly because “the world’s first sub-1nm chip” makes for an irresistible headline.

But the silicon beneath the headline deserves attention.

Nanostack shows how semiconductor progress is changing. The next era will not be defined solely by shrinking individual features across a flat surface. It will combine vertically stacked transistors, backside power delivery, gate-all-around structures, chiplets, advanced packaging, 3D memory and faster interconnects. Compute, memory, power and communications will increasingly be rearranged around one another in three dimensions.

That is the real meaning of IBM’s breakthrough.

Moore’s Law did not end when conventional scaling became more difficult. It changed direction. The industry spent decades building smaller across the X and Y axes. Now it is building upward along the Z axis.

The semiconductor future will not be found in one more decimal point. It will be stacked on top of itself.