AMD is taking a pragmatic approach to quantum computing by expanding its chip strategy around hybrid architectures that combine quantum processors with traditional high performance computing infrastructure. The company’s focus aligns with a widely held view that fault-tolerant quantum computing, while offering enormous potential, remains a long-term goal.

The company said quantum computing is evolving from laboratory research into a strategic technology area attracting investment from governments and enterprises. That trend gained major momentum following the US Department of Commerce’s announcement in May of more than $2 billion in funding for quantum computing and quantum manufacturing initiatives.

Rather than positioning quantum computers as replacements for conventional systems, AMD is emphasizing a model in which quantum processors operate as specialized accelerators alongside CPUs, GPUs, FPGAs and AI infrastructure.

“Quantum hardware has crossed the line from science to engineering over the past two years,” Brendan Burke, Research Director at Futurum, told Techstrong Semi.

“AMD’s two decades of HPC leadership position it to collaborate with what is fast becoming a distinct computer science discipline rather than a physics experiment. We believe quantum-classical infrastructure is a $10 billion opportunity by 2029 at the current pace of capital deployment, which makes AMD’s window to claim a leadership position a medium-term play, not a long-term bet.”

Providing the Classical Infrastructure

AMD’s approach focuses on providing the classical infrastructure required to support hybrid workloads. The company highlighted its EPYC server processors for orchestration and high-performance computing tasks, Instinct GPU accelerators for simulation and AI-assisted research, and FPGA and adaptive computing technologies for low-latency control and real-time error correction.

The company is also extending its ROCm software platform beyond traditional HPC environments. ROCm, originally developed to manage GPU-based workloads, is being adapted to support orchestration of quantum accelerators within hybrid computing environments.

The company also pointed to recent advances in quantum simulation as evidence that classical infrastructure remains a critical component of progress. AMD touted its Alveo accelerator technology as delivering up to 30-fold improvement in certain quantum simulation workloads. The key point here is that simulation environments allow researchers to test and refine quantum algorithms before deploying them on physical quantum hardware.

Distributing Workloads Across Multiple Processor Types

AMD’s emphasis on hybrid computing mirrors how today’s supercomputing systems already distribute workloads across multiple processor types. In this model, quantum processors are expected to handle specific calculations where quantum advantages may emerge, while classical infrastructure manages the surrounding computational processes.

AMD said this architecture will become more important as organizations pursue quantum applications in chemistry, materials science, drug discovery, energy research and optimization.

Supporting a diverse range of quantum technologies is another element of AMD’s strategy. Rather than aligning itself with a single quantum computing approach, the company is building infrastructure intended to support multiple quantum systems, including superconducting, trapped-ion, neutral-atom and photonic systems.

This flexibility could prove crucial in an emerging sector where no consensus exists around which quantum architecture will ultimately dominate.

AMD is also working with organizations across quantum development. Its collaborations include projects with JPMorganChase, Oak Ridge National Laboratory and IBM focused on integrating quantum systems with AI and high-performance computing environments.

The partnership with IBM is particularly focused on quantum-centric supercomputing architectures that combine quantum processors, AI resources and conventional HPC infrastructure within a unified platform.