TSMC Lays Out ‘Three-Layer Cake’ Vision for AI Chips

Taiwan Semiconductor Manufacturing Company (TSMC) is laying out a vision for the future of chip design that is built on a platform of three integrated technologies rather than keeping them separate.

The new paradigm was introduced at the 2026 Technology Symposium in Hsinchu, Taiwan, by TSMC Senior Vice President Zhang Xiaoqiang. The three-layer cake consists of the integration of compute, 3D integration packaging, and photonics optical transmission.
 
The move reflects a significant change in the way AI is processed compared with traditional computing. The technologies need to be integrated to work together, especially given that AI performance is network sensitive and not necessarily computing sensitive.

The layers are as follows:

Layer 1 – Compute: TSMC’s advanced nodes (N2, A16) are the foundation of all premium AI chips. The N2 node refers to TSMC’s 2nm process technology, which began mass production in Q4 2025. TSMC reportedly has already received about 25 tape outs of N2 products and is in the planning stages for more than 70 additional customer designs.

Layer 2 – 3D Integration: Emphasis on TSMC Chip-on-Wafer-on-Substrate (CoWoS). It’s an advanced semiconductor packaging technology developed by TSMC that allows multiple chips to be combined into a single high-performance package. TSMC’s CoWoS capacity is set to grow ~85% YoY in 2026 and 60% in 2027.

Layer 3 – Connectivity: TSMC will increase its use of Compact Universal Photonic Engine (COUPE), which is designed to address moving data between chips efficiently, one of the biggest future AI bottlenecks.

According to Xiaoqiang, global chip revenue is expected to reach $1 trillion this year, four years ahead of the previous forecasts. By 2030, the market is expected to be worth $1.5 trillion, with AI and high-speed computing accounting for 55% of this figure.

But don’t be fooled. This vision laid out by TSMC benefits TSMC the most, because they play in all three layers. Larger AI chips mean more advanced wafers, which in turn means more CoWoS and SoIC. That also means more optical integration.