Samsung and SK hynix are pursuing decidedly different strategies to overcome the bandwidth, power, and thermal limitations facing high bandwidth memory (HBM) as AI accelerators become increasingly powerful.
At Hot Chips 2026, Samsung outlined a roadmap that moves from conventional HBM to custom HBM and ultimately to a more radical architecture called zHBM. SK hynix, meanwhile, focused on advanced packaging and thermal-management technologies, while also evaluating Intel’s EMIB packaging technology for future HBM products.
Samsung’s roadmap, as reported by Serve the Home, begins with custom HBM, or cHBM, which adds substantially more logic to the memory base die than conventional HBM. Samsung’s cHBM approach uses more advanced logic processes to incorporate SoC-like functionality, potentially allowing some workloads to be moved from the main AI processor to the memory subsystem.
The downside is thermal density. Concentrating additional logic into the HBM base die creates localized hotspots that can become considerably difficult to cool. Samsung’s solution is a technology called Heat Path Block, or HPB. Designed for cHBM4, it is intended to reduce peak temperatures by more than 35%.
The company’s longer-term solution is zHBM, a whole new design. Rather than placing HBM beside the processor like Nvidia, AMD, and other AI accelerators do now, Samsung proposes vertically stacking HBM directly on top of the processor. This shortens the distance data must travel while eliminating the conventional silicon interposer.
Samsung says zHBM can eliminate overhead from unnecessary circuitry, lowering the power required to move data between memory and the processor. The problem, however, is that heat builds up and this design becomes much more difficult to cool than standard HBM designs.
Still, Samsung is making some pretty grand claims. It says that zHBM could deliver 70% higher power efficiency and 230% greater DRAM bandwidth compared with a conventional HBM4e stack. Samsung also says the architecture could free up another 8.3% of system power for the accelerator itself.
For its part, SK hynix is taking a somewhat different approach. Rather than emphasizing a radically different memory architecture, the company used its Hot Chips presentation (on-site reporting by WccfTech) to discuss the impact of thermal stress on HBM stacks.
The company is particularly interested in finding ways to control the heat generated inside increasingly dense HBM packages. Its answer includes a technology called iHBM. Similar in concept to Samsung’s HPB, iHBM places a highly thermally conductive but electrically insulating material within the HBM die-to-die PHY region, close to localized hotspots.
SK hynix says the approach can create a dedicated heat path and reduce thermal resistance by more than 30%. The company plans to introduce the technology into future HBM generations such as HBM5.
Perhaps the most notable development from SK hynix’s presentation was its inclusion of Intel EMIB in its HBM packaging roadmap. EMIB uses small silicon bridges embedded in a package substrate to connect adjacent dies, providing an alternative to the large silicon interposers used in conventional 2.5D designs.
The next HBM battle is increasingly about packaging. The contrasting approaches from Samsung and SK hynix reveal a shift in the AI semiconductor industry. HBM development is no longer simply about increasing DRAM capacity and bandwidth. As stacks become taller and AI processors consume more power, new challenges emerge that have to be addressed.
One has to wonder what AMD thinks of all of these machinations, because AMD is the developer and inventor of HBM. Thus far it has remained silent on the divergent courses (or forking, depending on your point of view) that HBM is taking.
